As CMOS technology (Complementary Metal Oxide Semiconductor) is scaled into a range of feature sizes smaller than 100 nm, the subthreshold currents and gate currents that occur in the CMOS field effect transistors increase on account of the reduced threshold voltages and the thin gate oxides of the CMOS field effect transistors. If an integrated CMOS circuit is in a non-active state, that is to say if the electrical signals at the inputs and the outputs of a CMOS circuit arrangement are constant with respect to time, then the leakage current components effect a static power loss leading to an undesirable discharge of the battery particularly in portable devices such as a mobile radio device (mobile phone) or a Personal Digital Assistant (PDA). The leakage current components in modern CMOS circuits are acquiring an increasing importance.
In a modern CMOS process there are usually a plurality of types of transistors with different threshold voltages and oxide thicknesses (cf. S. F. Huang et al., High performance 50 nm CMOS devices for microprocessor and embedded processor core applications, Technical Digest. International Electron Devices Meeting 2001, pages 11.1.1 to 11.1.41). If reducing the leakage currents (for example, upper limit: IOFF=10 pA/μm transistor width at T=25° C.) is a primary aim of the circuit design, CMOS field effect transistors with thicker gate oxide (for example, gate oxide layer thickness=2.3 nm instead of gate oxide layer thickness=1.6 nm for a 90 nm CMOS process) are used. However, this requires a higher supply voltage (VDD=1.2 V instead of VDD=1.0 V) and at the same time causes the propagation time of the logic gates with CMOS field effect transistors with thicker gate oxide to increase by up to a factor of 2 in comparison with a solution with CMOS field effect transistors with thin gate oxide.
To summarize, it should be noted that the trade-off between achieving a high switching speed of the CMOS circuit arrangement and a low active power consumption (˜CL VDD2), on the one hand, and small leakage currents in the CMOS field effect transistor on the other hand, precisely from the standpoint of mobile applications, is one of the greatest challenges facing future CMOS-based microelectronics.
Technology solutions possibilities such as new gate dielectrics or other transistor concepts are not yet available for example for 90 nm and 65 nm CMOS technology. For this reason, technology-close circuit design must be used to find solutions at the gate level which can be implemented with the given prerequisites of a modern system-on-chip technology.
Various solutions concepts are known for reducing leakage currents in CMOS field effect transistors.
A first solution concept is based on low-leakage-current standard cell libraries (present-day standard solution).
Special standard cell libraries whose gates include transistors with thicker oxide and high threshold voltages are used for circuit components in which a defined total leakage current budget constitutes the limiting boundary condition in the circuit design.
This solution includes the increased supply voltage and the higher gate propagation time, as was explained above. Usually, in the context of mixed solutions, all time-noncritical signal paths are constructed from the low-leakage-current gates, while the time-critical signal paths include fast gates with high leakage currents. However, this mixing of different types of gates in one circuit block has the effect that the fast gates in the time-critical signal paths, numbering approximately 5%, generate up to 50% of the total leakage current in the CMOS circuit arrangement.
A second solution concept involves providing low-leakage-current power switches in conjunction with low-VT standard cell libraries.
In this method for reducing the total leakage current, logic gates are formed from transistors with a low threshold voltage and thin gate oxide (so-called low-VT transistors, LVT) and are isolated from the real supply voltage VDD or from the real ground VSS in the standby state by power switches. The power switch or the power switches are embodied as transistors with a high threshold voltage and thick gate oxide (so-called low leakage device, LLD), as illustrated in FIG. 9 (cf. T. Inukai et al., Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration, Proceedings of the Custom Integrated Circuits Conference, pages 409-412, 2000).
FIG. 9 illustrates a CMOS circuit arrangement 900 having a CMOS circuit 901 containing NMOS field effect transistors 902 and PMOS field effect transistors 903, all the field effect transistors 902, 903 in each case having a thin gate oxide and a low threshold voltage. The CMOS circuit 901 is coupled to an operating potential VDD 904, on the one hand, and to a virtual ground node 905, on the other hand. A power switch transistor 906 having a thick gate oxide and a high threshold voltage is connected between the virtual ground node 905 and the ground potential 907.
All the leakage current components of the LVT block, that is to say of the CMOS circuit 901, can essentially be eliminated by this means. In a 90 nm CMOS technology platform, this method enables the leakage current to be reduced by three to four decades.
This method includes the long activation phase (10 to 100 ms compared with 1 ns clock period) before and after the switch-on of the power switch transistor 906. This prevents a fast change between an active state and the state with a reduced static power consumption. If a plurality of circuit blocks are situated on an electronic chip, then it must additionally be taken into account that the operation of active circuit blocks, by the switch-on of one or a plurality of circuit blocks, is not impaired by a collapse of the global voltage supply.
A third solution concept that is known is to alter the threshold voltage by means of a body bias voltage or substrate bias voltage.
This solution, which is also referred to as an “active well concept” or “variable VT concept”, is based on the substrate control effect of the CMOS field effect transistors, by means of which the threshold voltage of the transistors can be increased or lowered during operation of a CMOS circuit. A distinction is made between the so-called reverse biasing of logic gates with a preferably low threshold voltage and the so-called forward biasing of logic gates including transistors having a high threshold voltage. In the case of reverse biasing, a negative (positive) voltage VBN<VSS(VBP>VDD) is applied to the bulk contact or the body contact of an NMOS (PMOS) field effect transistor. In contrast thereto, in the case of forward biasing, the voltage 0.6V>VBN>0V(VDD>VBP>VDD−0.6V) is applied to the bulk contact or the body contact of an NMOS (PMOS) field effect transistor.
In general, the active well concept can only be used efficiently if the substrate control effect is sufficiently large. Since the substrate control effect for reverse biasing is reduced in accordance with γ˜1/COX−tOX with the reduction of the gate oxide layer thickness tOX, reverse biasing is ruled out in the medium term for transistors with a minimal channel length, as is described in Shih-Fen Huang et al., Scalability and Biasing Strategy for CMOS with Active Well Bias, 2001 Symposium on VLSI Technology Digest of Technical Papers. Reverse biasing additionally requires the provision of voltages that are higher than the supply voltage VDD or lower than the ground potential VSS. The associated additional outlay (that is to say the provision of additional charge pumps) must consequently be taken into account in the overall power budget. The maximum permissible negative (positive) body potential for NMOS transistors or PMOS transistors is limited by the gate induced drain leakage (band-to-band tunneling at the drain terminal).
For the “65 nm” technology generation, reverse biasing is ruled out for leakage current reduction in particular for thin, nitrided gate oxides having a gate oxide layer thickness of less than 1.5 nm EOT, since the gate leakage current relevant there cannot be influenced by a shift in the threshold voltage. The availability of a high-k dielectric would change this basic condition. However, an introduction can be expected at the earliest in the “45 nm” technology generation.
The linearized substrate control effect for MOS transistors with pocket implantations or halo implantations is approximately ΔVT≈0.5 VT0 in the case of forward biasing and is thus likewise reduced proportionally to the threshold voltage VT0 with each technology generation (cf. Shih-Fen Huang et al., Scalability and Biasing Strategy for CMOS with Active Well Bias, 2001 Symposium on VLSI Technology Digest of Technical Papers).
Therefore, forward biasing is of interest particularly for accelerating logic circuits which are constructed from LLD transistors having a relatively high threshold voltage (VT≈400 mV). Forward biasing results here in a performance gain of approximately 7% at the nominal supply voltage of VDD=1.2 V. The performance gain increases to approximately 30% at a reduced supply voltage of VDD=0.7 V.
The use of forward biasing is less efficient for a circuit including transistors having a low threshold voltage (VT≈200 mV). In general, the substrate voltage in the case of forward biasing is limited by the exponentially rising PN junction leakage currents to the range VBN<0.5 V (NMOS transistor) or VBP>VDD−0.5 V (PMOS transistor). Above this value, the PN junctions in the respective transistor become conducting.
A fourth solution concept that is known is to apply a leakage-current-minimizing bit pattern (so-called minimum leakage vector).
The basis of this concept is the bit pattern dependence of the leakage current in a CMOS logic gate having a plurality of inputs and series circuits (stack effect) of CMOS transistors. The leakage currents of a logic gate may differ depending on the bit pattern by a factor of 10 to 20 depending on the number of CMOS transistors situated in series, that is to say connected in series, and depending on the dimensionings of the CMOS transistors.
Ideally, in a circuit block including N logic gates, all N logic gates would be in the state with minimal leakage current. For this purpose, at the beginning of the standby state, a special bit pattern is fed into the input registers of a complex logic circuit block (for example, 16-bit multiplier, 32-bit adder, digital filter, etc.) and the clock is switched off.
This bit pattern is valid at the input of the logic gates for the duration of the non-active state.
Since CMOS circuits include a large number of cascaded logic gates which are arranged in many divergent and convergent signal paths, for a circuit block of this type the minimum leakage current can be set only with difficulty via the application of a bit pattern. The main difficulty consists in actually determining the bit pattern with the minimum leakage current in the case of, for example, 2×32 bit input vectors and blocks having a depth of 8 to 20 cascaded logic gates.
However, the method enables the fast activation and reactivation of a logic block (few clock cycles). This results in a higher flexibility in comparison with the solution with the power switches.
Furthermore, a static logic with monotonic logic transitions is known in F. Murabayashi et al., 2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor, IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, pages 972 to 980, July 1996 and A. Solomatnikov, D. Somasekhar, K. Roy, Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family, Proc. of 26th European Solid-State Circuits Conference (ESSCIRC), 19-21 Sep. 2000. The aim of the circuits in accordance with F. Murabayashi et al., 2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor, IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, pages 972 to 980, July 1996 and A. Solomatnikov, D. Somasekhar, K. Roy, Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family, Proc. of 26th European Solid-State Circuits Conference (ESSCIRC), 19-21 Sep. 2000 is to provide a robust high-speed logic for microprocessors as a replacement for the so-called dynamic domino logic, which is susceptible to interference.
Furthermore, D. Harris, M. A. Horowitz, Skew-Tolerant Domino Circuits, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pages 1702-1711, November 1997 describes a clock scheme for a pipeline stage in accordance with the “skew-tolerant domino” principle.
US 2003/0052371 A1 describes a circuit arrangement using static CMOS circuit technology in which a power switch is provided locally for a respective logic gate, the respective logic gate having NMOS field effect transistors and PMOS field effect transistors having identical threshold voltages.
U.S. Pat. No. 6,590,425 B2 describes a circuit arrangement having a logic function block including NMOS field effect transistors that provides a logic function and having a logic function block including PMOS field effect transistors that provides the logic function. Furthermore, a first clock transistor is connected between the logic function block including NMOS field effect transistors and the ground potential and a second clock transistor is connected between the operating potential and the outputs of both logic function blocks. All the transistors in the circuit arrangements in accordance with U.S. Pat. No. 6,590,425 B2 have the same threshold voltage and the same oxide layer thicknesses.
US 2002/0009013 A1 describes an interface circuit for a high-speed semiconductor device.
U.S. Pat. No. 6,329,874 B1 describes a circuit arrangement having a leakage current control transistor, to which an amplified gate driver signal is applied during an active mode.